1. Technical Field
The present invention relates, in general, to integrated circuit technology and, in particular, to the design of very large-scale integrated circuits. More particularly the present invention relates to the design of fast dynamic logic circuits. Still more particularly, the present invention relates to domino logic circuitry and to random-access memory circuit designs having memory cells that are undisturbed during cell-access time periods.
2. Description of the Related Art
Dynamic logic cells which are maintained in integrated circuits in a space-efficient and wireable fashion, and which are undisturbed during certain cell-access time periods is a goal sought by designers of very large-scale integrated circuits. In the design of integrated circuits utilizing dynamic logic cells, particularly register memory arrays, it is highly desirable to employ circuits having a minimal number of active devices per stage. This reduces the cost of dynamic logic circuits, when realized in integrated-circuit form, and results in higher packing density in view of the reduced area occupied per stage. It is also highly desirable to promote faster read and write operations for dynamic logic cells utilized in random-access memory designs. This reduces delay in processing which, in turn, increases performance.
It is well-known that complex logic functions can be implemented with shorter latency and smaller layout area by using dynamic logic rather than static logic. A wellknown example of a technique utilizing dynamic logic is "DOMINO" (hereinafter referred to as "domino"). This technique employs clocked transistors for precharging, a pull-down network having signal inputs, a clock input for discharging, and an inverter for buffering inverting an output signal. Due to the inversion of the output signal, it is possible to feed the output of such a domino logic circuit to the input of another domino logic circuit, and multiple logic levels can be connected for computation during the same evaluation clock phase.
Domino logic circuits use MOS (metal oxide silicon) transistors in their evaluation networks, resulting in a small layout available for design. Domino logic circuits are principally utilized for the implementation of non-inverting logic functions reduced to a combination of AND, OR, OR/AND or AND/OR gates. An advantage of domino logic is that it can be used to implement multiple levels of logic during a single evaluation clock phase very quickly, while still maintaining an acceptable noise immunity on intermediate nodes. This is partly due to the use of inverters between logic stages.
Random-access memory designs typically utilize MOS structures in conjunction with dynamic logic cells. Random-access memory is semiconductor-based memory that can be read and written by a microprocessor or other hardware devices. The storage locations in a random-access memory can be accessed in any order. Dynamic randomaccess memory can have as few as one integrated transistor and one capacitor component. Thus, a large number of random-access memory cells can be fabricated in a small wafer area. However, because dynamic random-access memory is volatile, the stored charge on the capacitor is required to be periodically refreshed, thereby requiring, in many instances, refresh circuitry. On the other hand, the memory-refresh requirements may be left to the programmer of the microcomputer to assure that all cells have been accessed in a prescribed period of time. Random-access memory at the chip level can be classified as memory having an access time independent of the physical location of data. This is contrasted with serial-access memories, which have some latency associated with the reading or writing of a particular datum, and with content-addressable memories.
In high-speed microcomputer applications which are computationally intensive, a large amount of on-chip memory is required. "Cycle-scaling" techniques commonly employed by programmers for memory-refresh purposes are thus limited. Also, dynamic random access memories are not easily integrated with microcomputers requiring read and write operations of different addresses within a single machine cycle. A four-phase microcomputer clocking system typically allows little or no time to refresh memory, so that the burden is placed on the programmer to ensure that an entire memory array included within a random-access memory chip is refreshed. In real-time applications, this constraint is highly undesirable. An unbalanced memory cell which includes transistors of varying size and type can assist in avoiding such "refreshment" by speeding write and read-time periods. However, this also contributes to an increase in read and write error conditions.
From the foregoing, it can be seen that a need exists for an improved memory array having dynamic-type cells adapted for high-density fabrication, and in which unbalanced static memory cells create a faster write into a register while eliminating error conditions commonly found in such unbalanced static memory cells. A need further exists to effectively write data into register cells in as short a time period as possible. A need also exists to incorporate such faster static memory cells into domino logic circuitry, while reducing errors associated with unbalanced static memory cells.